Example embodiments relate to memory modules, and more particularly, to a memory module providing high reliability while reducing the number of constituent elements, and an on-die termination setting method thereof.
As a semiconductor manufacturing process and a circuit technology have been developed, the bandwidth of DRAM chips is increasing and a transmission method of data is constantly in development. An increase of memory bandwidth may be directly related to an operation speed of an input/output interface circuit. The operation speed of an input/output interface circuit may be determined by signal integrity of a signal channel (DQ, DQS) and a timing margin of a transmission/reception circuit.
SDRAM, DDR1 SDRAM, DDR2 SDRAM and DDR3 SDRAM having multi drop bus structures have been developed to bandwidths of 333 Mbps, 400 Mbps, 800 Mbps and 1600 Mbps respectively. These types of memory systems may adopt a stub series terminated logic (SSTL) method as an input/output signaling method to improve signal integrity. According to that technology, a reflected wave causing mutual signal interference is generated because of impedance mismatch in a stub and thereby inter symbol interference (ISI) is generated. As a result, a reflected wave causing mutual signal interference seriously damages signal integrity, and a technology for suppressing a reflected wave may be used to reduce the signal interference.